Advances in Computer Technology and Applications in Japan by T. Watanabe (auth.), Thiruvalam K. S. Murthy, Carlos A.

By T. Watanabe (auth.), Thiruvalam K. S. Murthy, Carlos A. Brebbia (eds.)

This publication comprises chapters written by way of eminent scientists at the most recent improvement in desktop expertise and applica- tions in Japan. the target of the publication is to supply an information of the massive advances being made through Japane- se scientists at the basic region of data know-how and within the so-called 5th iteration computers. within the first bankruptcy, Watanabe of the NEC company, descri- bes complicated structure and expertise of supercomputing platforms. This topic is by means of Nakamura of Tohoku Uni- versity within the subsequent bankruptcy. one other form of supercomputer for vector processing, the FACOM vice president 2000 sequence is then des- cribed by means of Uchida ofFujitsu Ltd in bankruptcy three. specialist platforms are provided within the subsequent chapters through Ue- no and Oomari of Tokyo Denki collage and by means of Koseki and Goto of the NEC company. very important purposes in com- puter pictures are defined in bankruptcy Six via Ishii and Mu- rakami of Fujitsu Laboratories. Hayahi from a similar Labora- tory then discusses neurocomputers in Japan. the ultimate chap- ter via Noguchi of Tohoku Universityillustrates a tremendous software in communications.

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Main StoraQe L _______________ _ Vector P,ocessinQ Unit [ .. ended Sto'Oi~e 32-128 MWords Fig. 7. Hitachi S-810/20 architecture. FPR ~ floating-point registers; GPR - general-purpose registers; VMR - vector mask registers. " Fig. 8. SX-2 System Configuration. input vector output I,-~ _-,-'--,2'~1~ ,--I input ~-2 . 1 --------- veclOr 84 t- + + + ~ H--1'_--1'--1'--1 2 1I n ) + ) (0) single pipeline 5 I R 6 2 H 7 3 I=l vector output vector r r r ----- 3 -2 ----- 0-1 t- • 5 1 6 2 7 3 8 4 (bl parollel pipeline input vector output vector O°--f' 0-) .

Then this relation can be written by a PARTOF arrow from A to Arch. The modeling concept is as follows. An arch itself is considered to be the principal element in representing an arch system. 2 A frame-based representation of an arch. Structure description(left) and component description(right). 3 A frame-based representation of an arch by connecting a structure description and component descriptions. 50 representation should be done around the arch element and the rest of the elements should be represented as components of it.

5. 1 Advanced LS Is; The logic circuits are designed using high-speed, high-density emitter-coupled-logic (ECL). Each ECL LSI can pack 15000 of 80 ps delay gates. 6 nano seconds access time are packed with 3500 logic gates together on the same chip. For the main storage, 1M-bit large-capacity static random access memory chips with 35 nano seconds access time were adopted. 37 Pig . 2 High Density Packaging; Pujitsu is the first to have introduced glass ceramics as a board material for greater transmission speed.

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